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INTEGRATED CIRCUITS
74F160A*, 74F161A, 74F162A*, 74F163A 4-bit binary counter
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification IC15 Data Handbook
1996 Jan 29
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
FEATURES
* Synchronous counting and loading * Two count enable inputs for n-bit cascading * Positive edge-triggered clock * Asynchronous Master Reset (74F161A) * Synchronous Reset (74F163A) * High speed synchronous expansion * Typical count rate of 130MHz * Industrial range (-40C to +85C) available
DESCRIPTION
4-bit binary counters feature an internal carry look-ahead and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock. The clock input is buffered. The outputs of the counters may be preset to High or Low level. A Low level at the Parallel Enable (PE) input disables the counting action and causes the data at the D0-D3 inputs to be loaded into the counter on the positive-going edge of the clock (provided that the setup and hold requirements for PE are met). Preset takes place regardless of the levels at Count Enable (CEP, CET) inputs.
A Low level at the Master Reset (MR) input sets all the four outputs of the flip-flops (Q0 - Q3) in 74F161A to Low levels, regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). For the 74F163A, the clear function is synchronous. A Low level at the Synchronous Reset (SR) input sets all four outputs of the flip-flops (Q0 - Q3) to Low levels after the next positive-going transition on the clock (CP) input (provided that the setup and hold time requirements for SR are met). This action occurs regardless of the levels at PE, CET, and CEP inputs. The synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate (see Figure 1). The carry look-ahead simplifies serial cascading of the counters. Both Count Enable (CEP and CET) inputs must be High to count. The CET input is fed forward to enable the TC output. The TC output thus enabled will produce a High output pulse of a duration approximately equal to the High level output of Q0. This pulse can be used to enable the next cascaded stage (see Figure 2). The TC output is subjected to decoding spikes due to internal race conditions. Therefore, it is not recommended for use as clock or asynchronous reset for flip-flops, registers, or counters.
TYPE 74F161A 74F163A
TYPICAL fMAX 130MHz
TYPICAL SUPPLY CURRENT (TOTAL) 46mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION 16-pin plastic DIP 16-pin plastic SO COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F161AN, N74F163AN N74F161AD, N74F163AD INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F161AN, I74F163AN I74F161AD, I74F163AD DRAWING NUMBER SOT38-4 SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D3 CEP CET CP PE MR SR TC Q0 - Q3 DESCRIPTION Data inputs Count Enable Parallel input Count Enable Trickle input Clock input (active rising edge) Parallel Enable input (active Low) Asynchronous Master Reset input (active Low) for 74F161A Synchronous Reset input (active Low) for 74F163A Terminal count output Flip-flop outputs 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.2mA 20A/0.6mA 20A/1.2mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state.
1996 Jan 29
2
853-0347 16300
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F161A PIN CONFIGURATION
MR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
74F163A PIN CONFIGURATION
SR CP D0 D1 D2 D3 CEP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC TC Q0 Q1 Q2 Q3 CET PE
SF00656
SF00657
74F161A LOGIC SYMBOL
3 4 5 6
74F163A LOGIC SYMBOL
3 4 5 6
9 7 10 2 1
PE CEP CET CP MR
D0
D1
D2
D3
9 7 TC 15 10 2
PE CEP CET CP SR
D0
D1
D2
D3
TC
15
Q0
Q1
Q2
Q3
1
Q0
Q1
Q2
Q3
VCC = Pin 16 GND = Pin 8
14
13
12
11
VCC = Pin 16 GND = Pin 8
14
13
12
11
SF00658
SF00659
74F161A LOGIC SYMBOL (IEEE/IEC)
1 9 7 10 2 R M1 G3 G4 C2 /1,3,4+ CTR DIV 16
74F163A LOGIC SYMBOL (IEEE/IEC)
1 9 7 10 2 2R M1 G3 G4 C2 /1,3,4+ CTR DIV 16
3 4 5 6
1,2 D
14 13 12 11 15
3 4 5 6
1,2 D
14 13 12 11 15
4 CT=15
4 CT=15
SF00660
SF00661
1996 Jan 29
3
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
STATE DIAGRAM
APPLICATIONS
+VCC
0
1
2
3
4 D0 D1 D2 D3
PE 15 5 CEP CET 14 6 CLOCK CP SR
74F163A
TC
Q0 Q1 Q2 Q3
13
7
12
11
10
9
8
SF00665
Figure 1. Maximum count modifying scheme Terminal count = 6
SF00664
H H = Enable count or L L = Disable count
PE CEP CET CP
D0 D1 D2 D3
PE CEP CET CP
D0 D1 D2 D3
PE CEP CET CP
D0 D1 D2 D3
PE CEP CET CP
D0 D1 D2 D3
PE CEP CET CP
D0 D1 D2 D3
74F163A
TC
74F163A
TC
74F163A
TC
74F163A
TC
74F163A
TC
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
SR Q0 Q1 Q2 Q3
CP
SF00666
Figure 2. Synchronous multistage counting scheme
74F161A MODE SELECT - FUNCTION TABLE
INPUTS MR L H H H H H CP X X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X OUTPUTS OPERATING MODE Qn L L H count qn qn TC L L (1) (1) (1) L Reset (clear) Parallel load Count Hold (do nothing)
1996 Jan 29
4
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F163A MODE SELECT - FUNCTION TABLE
INPUTS SR l h h h h h H h L l qn X (1) (2) = = = = = = = = = CP X X CEP X X X h l X CET X X X h X l PE X l l h h h Dn X l h X X X OUTPUTS Qn L L H count qn qn TC L L (2) (2) (2) L OPERATING MODE Reset (clear) Parallel load Count Hold (do nothing)
High voltage level High voltage level one setup prior to the Low-to-High clock transition Low voltage level Low voltage level one setup prior to the Low-to-High clock transition Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition Don't care Low-to-High clock transition The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A) The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)
74F161A LOGIC DIAGRAM
CP MR 2 1
PE CET CEP D0
9 10 7 3 DRQ
CP
Q
14
Q0
D1
4 DRQ
CP
Q
13
Q1
D2
5 DRQ
CP
Q
12
Q2
D3
6 DRQ
CP
Q
11
Q3
15 VCC = Pin 16 GND = Pin 8
TC
SF00662
1996 Jan 29
5
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
74F163A LOGIC DIAGRAM
CP SR 2 1
PE CET CEP D0
9 10 7 3 D Q
CP
Q
14
Q0
D1
4 D Q
CP
Q
13
Q1
D2
5 D Q
CP
Q
12
Q2
D3
6 D Q
CP
Q
11
Q3
15
TC
VCC = Pin 16 GND = Pin 8
SF00663
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Commercial range Operating free-air temperature range free air Storage temperature range Industrial range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA C C C
1996 Jan 29
6
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Commercial range Operating free-air temperature range free air Industrial range 0 -40 PARAMETER MIN 4.5 2.0 0.8 -18 -1 20 +70 +85 NOM 5.0 MAX 5.5 UNIT V V V mA mA mA C C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VCC = MIN, VIL = MAX, , , VIH = MIN VCC = MIN, VIL = MAX, , , VIH = MIN VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V CET, PE IIL IOS ICC Low-level Low level input current Short-circuit output current3 Supply current (total) ICCH ICCL others VCC = MAX, VI = 0 5V MAX 0.5V VCC = MAX VCC = MAX -60 42 49 LIMITS MIN TYP2 MAX UNIT V 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -1.2 -0.6 -150 55 65 V V V V A A mA mA mA mA mA
VO OH
High-level High level output voltage
IO = MAX OH
10%VCC 5%VCC 10%VCC 5%VCC
2.5 2.7
VO OL VIK II IIH
Low-level Low level output voltage Input clamp voltage Input current at maximum input voltage High-level input current
IO = MAX OL
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
1996 Jan 29
7
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
AC ELECTRICAL CHARACTERISTICS
LIMITS TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF RL = 500 MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum clock frequency Propagation delay CP to Qn (PE = High) Propagation delay CP to Qn (PE = Low) Propagation delay CP to TC Propagation delay CET to TC Propagation delay MR to Qn Propagation delay MR to TC 'F161A 'F161A Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 2 Waveform 3 Waveform 3 100 2.0 4.0 2.0 3.5 5.0 4.5 1.5 2.5 6.0 5.0 TYP 130 4.0 6.5 4.5 5.5 7.5 7.5 3.5 5.0 8.5 8.5 6.5 10.0 6.5 8.5 10.5 10.5 6.5 7.5 12.0 10.0 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 90 2.0 4.0 2.0 3.5 5.0 4.0 1.5 2.5 5.5 5.0 7.0 11.0 7.5 9.5 11.5 11.5 7.0 8.0 13.0 11.0 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 75 2.0 4.0 2.0 3.5 5.0 4.0 1.5 2.5 5.5 5.0 7.0 11.0 7.5 9.5 11.5 11.5 7.0 8.0 13.0 11.0 MAX MHz ns ns ns ns ns ns
SYMBOL
PARAMETER
UNIT
AC SETUP REQUIREMENTS
LIMITS TEST CONDITION Tamb = +25C VCC = +5.0V CL = 50pF RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tw(L) tw(L) tREC Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low PE or SR to CP Hold time, High or Low PE or SR to CP Setup time, High or Low CET or CEP to CP Hold time, High or Low CET or CEP to CP CP pulse width (Load) High or Low CP pulse width (Count) High or Low MR pulse width Low Recovery time MR to CP 'F161A 'F161A Waveform 6 Waveform 6 Waveform 5 or 6 Waveform 5 or 6 Waveform 4 Waveform 4 Waveform 1 Waveform 1 Waveform 3 Waveform 3 5.0 5.0 0 0 9.0 6.5 0 0 10.5 6.0 0 0 4.0 5.0 4.0 6.0 4.5 6.0 TYP Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 5.0 5.0 0 0 9.5 7.0 0 0 10.5 7.0 0 0 4.0 5.5 4.0 7.0 4.5 6.5 Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF RL = 500 MIN 5.0 5.0 0 0 9.5 7.0 0 0 10.5 7.0 0 0 4.0 7.0 4.0 7.0 4.5 6.5 ns ns ns ns ns ns ns ns ns ns
SYMBOL
PARAMETER
UNIT
1996 Jan 29
8
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
AC WAVEFORMS
For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX
CP
VM tw(H) tPLH
VM tw(L)
VM tPHL
CET
VM tPLH
VM tPHL
Qn, TC
VM
VM
TC
VM
VM
SF00667
SF00668
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
Waveform 2. Propagation Delay, CET Input to TC Output
tw(L) MR VM VM CEP tREC CET VM tPHL CP VM ts(H) VM th(H) VM ts(L) VM th(L)
CP
VM
VM
Qn, TC
VM
SF00669
SF00670
Waveform 3. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Recovery Time
Waveform 4. CEP and CET Reset Setup and Hold Times
Dn
VM ts
VM th
SR
VM ts(L)
VM th(L)
VM ts(H)
VM th(H)
PE
VM ts(L)
VM th(L)
VM ts(H)
VM th(H)
CP
VM
VM
CP
VM
VM
SF00671
SF00672
Waveform 5. Synchronous Reset Setup and Hold Times
Waveform 6. Parallel Data and Parallel Enable Setup and Hold Times
1996 Jan 29
9
Philips Semiconductors
Product specification
4-bit binary counters
74F161A, 74F163A
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
1996 Jan 29
10
Philips Semiconductors
Product specification
4-bit binary counters
74F160A*, 74F161A, 74F162A*, 74F163A
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
1996 Jan 29 11
Philips Semiconductors
Product specification
4-bit binary counters
74F160A*, 74F161A, 74F162A*, 74F163A
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
1996 Jan 29 12
Philips Semiconductors
Product specification
4-bit binary counters
74F160A*, 74F161A, 74F162A*, 74F163A
NOTES
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
1996 Jan 29 13
Philips Semiconductors
Product specification
4-bit binary counter
74F160A*, 74F161A, 74F162A*, 74F163A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05084
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Philips Semiconductors
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